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are 8k bytes in size, filling the program memory space from address
FLASH byte block. In-system programming and standard parallel
0 through 3FFF hex. The final three blocks are 16k bytes in size and
programming are both available. On-chip erase and write timing
occupy addresses from 4000 through FFFF hex.
generation contribute to a user friendly programming interface.
The 89C51RC+ contains 32k bytes of FLASH program memory,
The 89C51RX+ FLASH reliably stores memory contents even after
which is organized as two blocks of 8k bytes, followed by one block
1000 erase and program cycles. The cell is designed to optimize the
of 16k bytes.
erase and programming mechanisms. In addition, the combination
Figure 41 depicts the FLASH memory configurations.
of advanced tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable cycling.
FLASH Programming and Erasure
The 89C51RX+ uses a 12.0V ±0.5V VPP supply to perform the
There are three methods of erasing or programming of the FLASH
Program/Erase algorithms.
memory that may be used. First, the FLASH may be programmed or
erased in the end-user application by calling low-level routines
through a common entry point in the Boot ROM. The end-user
FEATURES
application, though, must be executing code from a different block
" FLASH EPROM internal program memory with Block Erase.
than the block that is being erased or programmed. Second, the
on-chip ISP boot loader may be invoked. This ISP boot loader will, in
" Internal 1k byte fixed boot ROM, containing low-level in-system
turn, call low-level routines through the same common entry point in
programming routines and a default serial loader. The Boot ROM
the Boot ROM that can be used by the end-user application. Third,
can be turned off to provide access to the full 64k byte FLASH
the FLASH may be programmed or erased using the parallel method
memory.
by using a commercially available EPROM programmer. The parallel
programming method used by these devices is similar to that used
" Boot vector allows user provided FLASH loader code to reside
by EPROM 87C51, but it is not identical, and the commercially
anywhere in the FLASH memory space. This configuration
available programmer will need to have support for these devices.
provides flexibility to the user.
" Default loader in Boot ROM allows programming via the serial port
Boot ROM
without the need for a user provided loader.
When the microcontroller programs its own FLASH memory, all of
the low level details are handled by code that is permanently
" Up to 64k byte external program memory if the internal program
contained in a 1k byte Boot ROM that is separate from the FLASH
memory is disabled (EA = 0).
memory. A user program simply calls the common entry point with
" Programming and erase voltage 12V ±0.5V. appropriate parameters in the Boot ROM to accomplish the desired
operation. Boot ROM operations include things like: erase block,
" Read/Programming/Erase:
program byte, verify byte, program security lock bit, etc. The Boot
Byte-wise read (100 ns access time).
ROM overlays the program memory space at the top of the address
space from FC00 to FFFF hex, when it is enabled. The Boot ROM
Byte Programming (20 ms).
may be turned off so that the upper 1k bytes of FLASH program
Typical erase times (including preprogramming time):
memory are accessible for execution.
Block Erase (8k bytes or 16k bytes) in 3 seconds.
Full Erase (64k bytes) in 3 seconds.
" Parallel programming with 87C51 compatible hardware interface
to programmer.
" In-circuit programming.
" Programmable security for the code in the FLASH.
" 1000 minimum erase/program cycles for each byte.
" 10 year minimum data retention.
1998 Sep 15 37
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family
89C51RC+/RD+
32K/64K ISP FLASH with 512 1K RAM
FFFF FFFF
BOOT ROM
FC00
(1k BYTES ON
BLOCK 4
ALL PARTS)
16k BYTES
C000
BLOCK 3
16k BYTES
PROGRAM
8000 89C51RD+
ADDRESS
BLOCK 2
16k BYTES
4000
89C51RC+
BLOCK 1
8k BYTES
2000
BLOCK 0
8k BYTES
0000
SU01041
Figure 41. FLASH Memory Configurations
Power-On Reset Code Execution Hardware Activation of the Boot Loader
The 89C51RX+ contains two special FLASH registers: the BOOT The boot loader can also be executed by holding PSEN LOW,
VECTOR and the STATUS BYTE. At the falling edge of reset, the EA greater than VIH (such as +12V), and ALE HIGH (or not
89C51RX+ examines the contents of the Status Byte. If the Status connected) at the falling edge of RESET. This is the same effect as
Byte is set to zero, power-up execution starts at location 0000H, having a non-zero status byte. This allows an application to be built
which is the normal start address of the user s application code. that will normally execute the end user s code but can be manually
When the Status Byte is set to a value other than zero, the contents forced into ISP operation.
of the Boot Vector is used as the high byte of the execution address
If the factory default setting for the Boot Vector (0FCH) is changed, it
and the low byte is set to 00H. The factory default setting is 0FCH,
will no longer point to the ISP masked-ROM boot loader code. If this
corresponds to the address 0FC00H for the factory masked-ROM
happens, the only way it is possible to change the contents of the
ISP boot loader. A custom boot loader can be written with the Boot
Boot Vector is through the parallel programming method, provided
Vector set to the custom boot loader.
that the end user application does not contain a customized loader
NOTE: When erasing the Status Byte or Boot Vector, that provides for erasing and reprogramming of the Boot Vector and
both bytes are erased at the same time. It is necessary Status Byte.
to reprogram the Boot Vector after erasing and
After programming the FLASH, the status byte should be
updating the Status Byte.
programmed to zero in order to allow execution of the user s
application code beginning at address 0000H.
1998 Sep 15 38
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family
89C51RC+/RD+
32K/64K ISP FLASH with 512 1K RAM
VCC
VPP +12V
RST
VCC +5V
TxD TxD
RxD RxD
XTAL2
VSS
XTAL1
VSS
SU01042
Figure 42. In-System Programming with a Minimum of Pins
bytes. The AAAA string represents the address of the first byte in
In-System Programming (ISP)
the record. If there are zero bytes in the record, this field is often set
The In-System Programming (ISP) is performed without removing
to 0000. The RR string indicates the record type. A record type of
the microcontroller from the system. The In-System Programming
00 is a data record. A record type of 01 indicates the end-of-file
(ISP) facility consists of a series of internal hardware resources
mark. In this application, additional record types will be added to
coupled with internal firmware to facilitate remote programming of
indicate either commands or data for the ISP facility. The maximum
the 89C51RX+ through the serial port. This firmware is provided by
number of data bytes in a record is limited to 16 (decimal). ISP
Philips and embedded within each 89C51RX+ device.
commands are summarized in Table 8.
The Philips In-System Programming (ISP) facility has made in-circuit
As a record is received by the 89C51RX+, the information in the
programming in an embedded application possible with a minimum
record is stored internally and a checksum calculation is performed.
of additional expense in components and circuit board area.
The operation indicated by the record type is not performed until the
The ISP function uses five pins: TxD, RxD, VSS, VCC, and VPP (see
entire record has been received. Should an error occur in the
Figure 42). Only a small connector needs to be available to interface
checksum, the 89C51RX+ will send an X out the serial port
your application to an external circuit in order to use this feature.
indicating a checksum error. If the checksum calculation is found to [ Pobierz całość w formacie PDF ]
